| HOLE TO PAD DESIGN GUIDLINES | |||||||||||||
The purpose of this document is to clarify the issues relating to clearance needs from hole to pad using figures based on standards developed by the Institute for Interconnecting and Packaging Electronic Circuits (IPC). The figures quoted are based on IPCâs Performance ãClass 3ä for high reliability electronic products and Design ãLevel Cä for high design complexity boards. General Requirements
All pads and therefore annular rings should be maximised wherever possible, consistent with good design practice and electrical clearance requirements. Annular Rings Requirements Minimum Annular Ring It is important to have some annularring left on the pad after manufacturing to avoid problems such as holewall pullaway, partial voids, partial solder joint, reduced clearance and soldermask in holes. Annularring problems Pad Requirements Minimum pad size = a + 2b + c
Allowing a 0.1mm positive tolerance on hole sizes for (a),0.05mm minimum annular ring requirement for(b) and 0.45mm fabrication allowance for pane lsup to 450mm long for (c),comes to a total of 0.65mm, meaning that a commonly specified 0.9mm hole requires a 1.55mm pad. This 0.65mm hole-to-pad clearance requirement is fine for 0.3mm (0.012") track & spacing designs running 1 track between pad on a conventional 2.54mm (0.1") pitch. It is, however, 0.05mm too high for the denser 0.2mm (0.008") track & spacing designs running 2 tracks between pads. Denser designs usually utilise surface mounted components where there are no hole to pad clearance problems other than for vias where the hole size is usually reduced to accommodate the smaller pad size.
Summary As stated it is possible to get hole breakout with a 0.5mm clearance, if all of the allowable variables are on maximum and in opposite directions. These variations include hole size over nominal by 0.1mm, pad width loss of 0.05mm, pattern location movement and/or film expansion of 0.1mm (to the left) and hole location movement of 0.05mm (to the right).
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